A sigma-delta analog-to-digital converter converts a voltage amplitude of an analog input signal into a corresponding digital value of a digital data stream. Where the minimum voltage amplitude of the analog input signal is a ground potential, the analog-to-digital converter (ADC) ideally converts the ground potential to a minimum digital value. If, for example, the ADC is a ten-bit ADC, then the minimum digital value would typically be a ten-bit digital value of ten digital zeros. The extent to which the digital value of the digital data stream of the ADC deviates from digital zero is referred to as “dc offset error.”
Where the maximum voltage amplitude of the analog input signal is a reference voltage, the ADC ideally converts the reference voltage to a maximum digital value. If the ADC is a ten-bit ADC, then the maximum digital value would typically be a ten-bit digital value of ten digital ones. The extent to which the digital value output by the ADC deviates from a digital value of all digital ones is referred to as “gain error.”
Moreover, any given voltage amplitude that lies between the ground potential and the reference voltage is ideally converted into a digital value that is the same proportion of the maximum digital value as the given voltage amplitude is of the reference voltage. In other words, a linearly increasing voltage amplitude is ideally converted by the ADC into a linearly increasing digital value. The extent to which the ADC receives an analog input signal with a linearly increasing voltage amplitude and outputs digital values that do not linearly increase in value is referred to as “integral non-linearity error” (INL error).
FIG. 1 (prior art) is a graph of digital values output by a hypothetical prior art ADC that receives an analog input signal having voltage amplitudes between zero volts and four volts. The actual, uncorrected digital values output by the ADC are shown as dashed curve 10. A correction value 11 is applied to each digital value output by the ADC to compensate for dc offset error. Although correction value 11 compensates for a positive dc offset error of the hypothetical ADC, dc offset error of other analog-to-digital converters can be negative. The digital output of the ADC for analog inputs having voltage amplitudes between zero and four volts, after compensating for dc offset error, is represented by dashed curve 12.
Secondly, each digital value output by the ADC is also corrected by proportionate values 13 to compensate for gain error. Thus, the proportionate values 13 increase with increasing voltage amplitude of the analog input signal. Although the hypothetical ADC compensates for gain error by multiplying the digital value output by the hypothetical ADC by a coefficient greater than one to obtain the proportionate values 13, gain error of other analog-to-digital converters can require correction by multiplying by a coefficient of less than one. Solid curve 14 represents the digital values output by the ADC for given voltage amplitudes of an analog input signal after correction for dc offset error and gain error. Finally, straight line 15 represents the digital values output by the ADC after correction for dc offset error, gain error and INL error.
There are various known prior art methods for correcting for dc offset error, gain error and INL error. A first prior art method involves testing each integrated circuit chip containing an ADC with external testing equipment. The external testing equipment produces an analog input signal having a precise voltage amplitude of zero volts. The amount by which the digital value of the output of the ADC differs from the minimum possible digital value is included in a lookup table as the dc offset error. In FIG. 1 (prior art), the minimum possible digital value is shown as digital zero. The testing equipment then produces an analog input signal having a precise voltage amplitude of the reference voltage, shown in FIG. 1 (prior art) as four volts. For an analog input signal having a voltage amplitude of four volts, the proportion by which the digital value of the output of the ADC differs from the maximum possible digital value is included in a lookup table as a coefficient representing the gain error. FIG. 1 (prior art) shows a maximum digital value of 1023, corresponding to the maximum possible digital value output by a ten-bit ADC. The coefficient is the factor by which each digital value of dashed curve 12 is multiplied to yield solid curve 14.
The external testing equipment in the first prior art method then produces a limited number of analog input signals having precise voltage amplitudes between zero and four volts. The resulting limited number of digital values of the output of the ADC are detected by a correction circuit of the ADC. The correction circuit corrects the digital values to account for dc offset error and gain error by the method described above. Then the corrected digital values are used mathematically to derive a polynomial curve, such as solid curve 14. A larger number of points from the polynomial curve are then included in the lookup table. Each of the larger number of points in the lookup table has a correction factor that is applied to its corresponding digital value output by the ADC. When the ADC operates, the actual digital output of the ADC is adjusted mathematically using values in the lookup table that account for dc offset error, gain error and INL error. The result is a corrected digital output approximating straight line 15.
The process of testing each integrated circuit ADC chip in the first prior art method using external testing equipment is both costly and time consuming.
A second prior art method involves manufacturing a voltage dividing network on each integrated circuit ADC chip. The voltage dividing network is then used to generate analog input signals having precise voltage amplitudes. Each resistor of the voltage dividing network can be trimmed using a laser to produce a more precise resistance. A lookup table with correction factors to account for dc offset error, gain error and INL error is then compiled in a manner similar to that of the first prior art method. Manufacturing the resistors of the voltage dividing networks and calibrating the resistors through trimming is, however, costly and time consuming.
An apparatus and a method are sought to calibrate an ADC to compensate for various types of error without using external testing equipment or on-chip voltage dividing networks to generate analog input signals with precise voltage amplitudes.